june 2010 doc id 15690 rev 1 1/8 AN2984 application note minimizing the set-related effects on the output of a voltage linear regulator introduction this application note deals with the effects of set (single event transient) on the rhfl4913a low-drop linear regulator. after a short description of the phenomenon, some solutions for coping with these effects are introduced and discussed. the rhfl4913a voltage regulator the rhfl4913a is an adjustable high-performance positive voltage regulator with exceptional radiation performance. it is tested in accordance with the mil std 883e method 1019.6, in eldrs conditions. the device is available in the flat-16 and the new smd5c hermetic ceramic package, as shown in figure 1 , and the qml-v die is specifically designed for space and harsh radiation environments. in figure 2 the internal block diagram is shown. figure 1. rhfl4913a packages smd5c flat-16 5-connection smd www.st.com
AN2984 2/8 doc id 15690 rev 1 the rhfl4913a operates with an input supply of up to 12 v. to adjust the output voltage, the r2 resistor must be connected between the v o and adj pins. the r1 resistor must be connected between the adj and ground. resistor values can be derived from the following formula: v o = v adj (r1 + r2) / r1 the v adj is 1.23 v, controlled by the internal temperature-compensated band-gap block. the minimum output voltage is therefore 1.22 v and the minimum input voltage is 3 v. the adjustable rhfl4913a is functional as soon as the (v i - v o ) voltage difference is slightly above the power element saturation voltage. the adj pin to ground resistor value must not be greater than 10 k , in order to keep the output feedback error below 0.2 %. a minimum of 0.5 ma i o must be set to ensure perfect no-load regulation. it is advisable to dissipate this current into the divider bridge resistor. all available v i pins, as well as all available v o pins, should always be externally interconnected, otherwise the stability and reliability of the device cannot be guaranteed. the inhibit function switches off the output current electronically, and therefore very quickly. according to lenz's law, external circuitry reac ts with ldi/dt terms, which can be of high amplitude where a serial coil inductance exists. large transient voltage would develop on both device terminals. it is advisable to protect the device with schottky diodes to prevent negative voltage excursions. in the worst case, a 14 v zener diode can protect the device input. the device has been desi gned for high stability and low dr opout operation. therefore, tantalum input and output capacitors with a minimum 1 f are mandatory. the esr capacitor range is from 0.01 to over 20 . this range is useful when esr increases at a low temperature. when large transient currents are expected, larger value capacitors are necessary. in the case of high current operation with short circuit events expected, caution must be exercised with regard to capacitors. they must be connected as close as possible figure 2. internal block diagram
AN2984 doc id 15690 rev 1 3/8 to the device terminals. as some tantalum capacitors may permanently fail when subjected to high charge-up surge currents, it is recommended to decouple them with 470 nf polyester capacitors. as the rhfl4913a adjustable voltage regulator is manufactured with very high speed bipolar technology (6 ghz f t transistors), the pcb layout must be designed with exceptional care, with very low inductance and low mutually coupling lines. otherwise, high frequency parasitic signals may be picked up by the devi ce resulting in syste m self-oscillation. the benefit is an svr performance extended to far higher frequencies. in order to replace a standard 3-terminal industry device, fixed voltage versions are available. a separate kelvin voltage sensing line provides the adj pin with exact load ?high potential? information. but variable remote load current consumption induces variable iq current (iq is roughly the i out current divided by the h fe of the internal pnp series power element) routed through the parasitic series line rw2 resistor. to compensate for this parasitic voltage, an rw1 resistor can be introduced to provide the necessary compensating voltage signal to the adj pin, as shown in figure 3 . in the case of an fpga power supply, as these devices are very sensitive to vdd transients beyond a small percentage of their nominal supply voltage (usually 1.5 v), special attention must be taken to mitigate possible heavy-ion disturbances. the worst case heavy-ion effect can be summarized as the following: the rhfl4913a internal control loop being cut (opened) or short-circuited for a sub-microsecond duration. during such an event, the rhfl4913a die power element can either provide excessive current or current supply stoppage to the output (v out ) for a duration of about one microsecond, after which time the voltage regulator smoothly recovers to nominal operation. to mitigate these ?transients?, it is recommended to firstly implement the pcb layout using the following notes: minimizing series/parallel parasitic inductances of the pc path; using a low esr 47 f tantalum v out filtering capacitor with a 470 nf ceramic capacitor in parallel with the former (to reduce dynamic esr); with this implementation, the eldo simulated worst transient case shows no more than a 90 mv deviation from the nominal line voltage value. figure 3. application schematic for remote load operation
mitigation technique for set AN2984 4/8 doc id 15690 rev 1 1 mitigation technique for set as we know, the characteristics of the voltage transient on the output of a voltage regulator, consequent to the transfer of energy related to an ion strike with the silicon, is a critical issue in space applications. large undershoot can cause erratic operations in memories and microprocessors, while overshoot of an excessive amplitude can lead to the degradation - or even the destruction - of cmos devices. for example, for most fpga the recommended operating voltage is 1.5 v with 1.6 v the maximum limit (in some applications it is restricted to 1.575 v to maintain a further safety margin). the latter applies to both static and dynamic operating conditions. the recommendations in this application note are based on the outcomes of an experimental analysis conducted at texas a&m university (cyclotron single event effects test facility on device behavior in a heavy ion environment). for mo re information please refer to ?see test report v3.0 - heavy ion see test of rhfl4913a from stmicroelectronics with set mitigation circuitry?, issued by nasa on november 18th, 2006. during these experiments, the configurations, illustrated in figure 4 and figure 5 , were found capable of reducing the set transient's characteristics on the voltage regulator output at a level acceptable for most critical applications, e.g. fpga supply. figure 4. baseline bias configuration with remote feedback v in r1 0.2 v out + _ 0.1 15 f 100nf 100nf 220 f r2 adj v i v o rhfl4913a c out am07 8 11v1
AN2984 mitigation technique for set doc id 15690 rev 1 5/8 each of the two options has its own advantages and drawbacks. in the scheme shown in figure 4 , as the r resistor is located between the voltage regulation output and the output voltage setting resistors, the regulation - especially with the load - is expected to be much better and thus the output voltage more precise compared to the second option; the latter option should have superior set immunity. for both configurations, the characteristics of the transients can be summarized as follows: 1. in many of the sets observed, both short (< 100 nsec) and long-duration (max 2 sec) pulses are present; 2. set cross-section increases with the let, as expected; 3. sets associated to the highest let are those with the longest transients (provided the other conditions are the same); 4. irrespective of the let, at a fixed v in = 3.3 v the max v out deviation measured is < 140 mv, using high-quality, low-esr, low-esl capacitors, (i.e., ceramic or tantalum); higher (v in -v out ) dropout increases the max v out excursion; 5. the short-duration pulses are mostly dependent on the esl of the capacitors used, and also dependent on the stray inductances. therefore, they cannot be suppressed by simply increasing the cap value. the only way to minimize them is with an action at board level. 6. in the scheme of figure 4 , all long-duration pulses can be suppressed by adding a capacitor of at least 60 f before the filter. even the set cross-section is limited, at least for let up to 53 mev*cm2/mg, as shown in figure 6 . figure 5. local feedback configuration am07 8 12v1 v in 0.2 v out + _ 15 f 100nf 0.1 220 f r1 r2 adj v i v o rhfl4913a 100nf c out
mitigation technique for set AN2984 6/8 doc id 15690 rev 1 as can be seen, the best solution recommended in critical applications is the one given in figure 4 , with an additional capacitor of at least 60 f connected before the rc filter. finally, some additional recommendations in order to minimize the output voltage glitches: a) use low esr (< 30 m ), low esl (10 - 20 nh) ceramic capacitors or others rated for high speed applications. b) esl can be reduced using an array of parallel capacitors. c) gnd: implement star bus topology or a plane. d) c in as close to v in - gnd pads as possible. e) a 10 nf cap between out and adj runs as an effective noise filter and improves stability; it is essential in remote sensing configuration. in conclusion, most sets can be mitigated by means of external components: input and output resistors, output series schottky diodes, and rc filters, resulting in greatly reduced set sensitivity and remaining sets with small amplitude (below 200 mv) and short duration (< 20 ns). figure 6. set cross-section vs. let diagram rhfl4913a ? + ? filter ? and ? other ? set ? mitigation rhfl4913a ? + ? filter ? and ? other ? set ? mitigation
AN2984 revision history doc id 15690 rev 1 7/8 2 revision history table 1. document revision history date revision changes 23-jun-2010 1 initial release.
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